General Information

  • target students: PhD students
  • period: spring semester
  • duration: 24 hours
  • language: English (optionally Italian, according to the students’ needs)
  • teacher: Carlo Sau

Registration

The course will be held in the first half of July (the almost final complete lecture schedule is available at the end of this page). In order to participate, it is necessary to send an e-mail to the course teacher at the e-mail address carlo.sau@unica.it.


Abstract

Due to the rise of heterogeneous Systems-on-Chip (SoCs), integrating in the same die general purpose and specialized accelerators with dedicated logic, Electronic Design Automation (EDA), for digital systems focused on logic synthesis and implementation, is moving to the next abstraction level. If Register Transfer Level (RTL) and Hardware Description Languages (HDL) are nowadays the most common way to describe system behavior, the route towards the adoption of higher level languages and more abstract specifications has already been planned and started. High Level Synthesis (HLS) takes common general purpose programming languages, mostly C, to deliver an RTL description of the system ready for the logic synthesis. Despite this, user intervention and lower level details knowledge are still required, having strong impact on the resulting system and, in the end, limiting the large adoption of this technique, demonstrating that HLS technology is in a good shape but not yet mature enough.


Goals

The course has the goal of providing motivations of HLS, laying on the evolution of SoCs into heterogeneous platforms, as well as on the increase of applications complexity and data amount.

The HLS flow is described and explored under several aspects, and different HLS solutions available in literature and in the market are analyzed. User knobs for driving HLS according to the specific requirements and goals are investigated, together with the impact on the resulting system.

Some HLS tools (Vivado HLS and CAPH) are adopted in the practice on a test case throughout the course, in order to better understand usage, potentials and limitations of such new technology solutions.


Syllabus

  1. Introduction [2h]
  2. HLS Basics [8h]
    1. Background
    2. HLS Flow
  3. HLS Tools [12h]
    1. HLS Features
    2. Vivado HLS
    3. CAPH
  4. Final Project [2h]

Requirements

  • Programming Languages
  • Digital Systems Design

Evaluation

  • Final Project (design of a specialized accelerator for an example application proposed by the student)

Lectures Schedule

  • Thursday, 01/07/2021: (9-11, 15-17), 4h
    • Introduction (9-11)
    • HLS Basics – Background (15-17)
    • HLS Basics – HLS Flow (15-17)
  • Monday, 05/07/2021: (9-11, 15-17), 4h
    • HLS Basics – HLS Flow (9-11)
    • HLS Basics – HLS Flow (15-17)
  • Wednesday, 07/07/2021: (9-11, 15-17), 4h
    • HLS Basics – HLS Flow (9-11)
    • HLS Tools – HLS Features (15-17)
    • HLS Tools – Vivado HLS (15-17)
  • Thursday, 08/07/2021: (9-11, 15-17), 4h
    • HLS Tools – Vivado HLS (9-11)
    • HLS Tools – Vivado HLS (15-17)
  • Friday, 09/07/2021: (9-11), 2h
    • HLS Tools – Vivado HLS (9-11)
  • Monday, 12/07/2021: (16-18), 2h
    • HLS Tools – CAPH (16-18)
  • Tuesday, 13/07/2021: (16-18), 2h
    • HLS Tools – CAPH (16-18)
  • Tuesday, 20/07/2021: (9-11), 2h
    • Final Project (9-11)