Power-Awarness in Coarse-Grained Reconfigurable Designs: a Dataflow Based Strategy

Title: Power-Awarness in Coarse-Grained Reconfigurable Designs: a Dataflow Based Strategy
Authors:  Francesca Palumbo, Carlo Sau and Luigi Raffo
Conference: 2014 IEEE International Workshop on Signal Processing Systems (SiPS)
Year: 2014
Abstract: Applications and hardware complexity management in modern systems tend to collide with efficient resource and power balance. Therefore, dedicated and power-aware design frameworks are necessary to implement efficient multi-functional runtime reconfigurable signal processing platforms. In this work, we adopt dataflow specifications as a starting point to challenge power minimization.
Presentation: SiPS_2014
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Export BibTex: PALUMBO_SIPS_2014


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