{"id":2161,"date":"2015-08-05T10:24:16","date_gmt":"2015-08-05T10:24:16","guid":{"rendered":"http:\/\/sites.unica.it\/rpct\/?page_id=2161"},"modified":"2016-07-25T08:31:14","modified_gmt":"2016-07-25T08:31:14","slug":"power-awarness-in-coarse-grained-reconfigurable-designs-a-dataflow-based-strategy","status":"publish","type":"page","link":"https:\/\/sites.unica.it\/rpct\/references\/power-awarness-in-coarse-grained-reconfigurable-designs-a-dataflow-based-strategy\/","title":{"rendered":"Power-Awarness in Coarse-Grained Reconfigurable Designs: a Dataflow Based Strategy"},"content":{"rendered":"<p><strong>Title<\/strong>: Power-Awarness in Coarse-Grained Reconfigurable Designs: a Dataflow Based Strategy<br \/>\n<strong>Authors<\/strong>:\u00a0 Francesca Palumbo, Carlo Sau and Luigi Raffo<br \/>\n<strong>Conference<\/strong>: 2014 IEEE International Workshop on Signal Processing Systems (SiPS)<br \/>\n<strong>Year<\/strong>: 2014<br \/>\n<strong>Abstract<\/strong>: Applications and hardware complexity management in modern systems tend to collide with efficient resource and power balance. Therefore, dedicated and power-aware design frameworks are necessary to implement efficient multi-functional runtime reconfigurable signal processing platforms. In this work, we adopt dataflow specifications as a starting point to challenge power minimization.<br \/>\n<strong> Presentation: <\/strong><a href=\"http:\/\/sites.unica.it\/rpct\/files\/2015\/08\/SiPS_2014.pdf\">SiPS_2014<\/a><br \/>\n<strong><a href=\"http:\/\/ieeexplore.ieee.org\/xpl\/articleDetails.jsp?arnumber=6986104\">Link to full text<\/a><br \/>\nExport BibTex:\u00a0<a href=\"http:\/\/sites.unica.it\/rpct\/files\/2016\/07\/SAU_SIPS_2014.txt\">PALUMBO_SIPS_2014<\/a><\/strong><\/p>\n<hr \/>\n<p><a href=\"http:\/\/sites.unica.it\/rpct\/references\/\">Return to publications<\/a><\/p>","protected":false},"excerpt":{"rendered":"<p>Title: Power-Awarness in Coarse-Grained Reconfigurable Designs: a Dataflow Based Strategy Authors:\u00a0 Francesca Palumbo, Carlo Sau and Luigi Raffo Conference: 2014 IEEE International Workshop on Signal Processing Systems (SiPS) Year: 2014 Abstract: Applications and hardware complexity management in modern systems tend to collide with efficient resource and power balance. Therefore, dedicated and power-aware design frameworks are &hellip; <a href=\"https:\/\/sites.unica.it\/rpct\/references\/power-awarness-in-coarse-grained-reconfigurable-designs-a-dataflow-based-strategy\/\" class=\"more-link\">Continua la lettura di <span class=\"screen-reader-text\">Power-Awarness in Coarse-Grained Reconfigurable Designs: a Dataflow Based Strategy<\/span> <span class=\"meta-nav\">&rarr;<\/span><\/a><\/p>\n","protected":false},"author":2529,"featured_media":0,"parent":1778,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-2161","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/sites.unica.it\/rpct\/wp-json\/wp\/v2\/pages\/2161","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/sites.unica.it\/rpct\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/sites.unica.it\/rpct\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/sites.unica.it\/rpct\/wp-json\/wp\/v2\/users\/2529"}],"replies":[{"embeddable":true,"href":"https:\/\/sites.unica.it\/rpct\/wp-json\/wp\/v2\/comments?post=2161"}],"version-history":[{"count":6,"href":"https:\/\/sites.unica.it\/rpct\/wp-json\/wp\/v2\/pages\/2161\/revisions"}],"predecessor-version":[{"id":2461,"href":"https:\/\/sites.unica.it\/rpct\/wp-json\/wp\/v2\/pages\/2161\/revisions\/2461"}],"up":[{"embeddable":true,"href":"https:\/\/sites.unica.it\/rpct\/wp-json\/wp\/v2\/pages\/1778"}],"wp:attachment":[{"href":"https:\/\/sites.unica.it\/rpct\/wp-json\/wp\/v2\/media?parent=2161"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}