{"id":1778,"date":"2014-06-03T08:42:39","date_gmt":"2014-06-03T08:42:39","guid":{"rendered":"http:\/\/sites.unica.it\/rpct\/?page_id=1778"},"modified":"2016-11-02T07:41:15","modified_gmt":"2016-11-02T07:41:15","slug":"references","status":"publish","type":"page","link":"https:\/\/sites.unica.it\/rpct\/references\/","title":{"rendered":"Publications"},"content":{"rendered":"

<\/p>\n

Year: 2010<\/a>, 2011<\/a>, 2012<\/a>, 2013<\/a>, 2014<\/a>, 2015<\/a>, 2016<\/a><\/h2>\n
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<\/a><\/p>\n

2016<\/strong><\/h3>\n

[C13] Power and Clock Gating Modelling in Coarse Grained Reconfigurable Systems
\n<\/a>Authors:<\/strong>\u00a0 Tiziana Fanni, Carlo Sau, Paolo Meloni, Luigi Raffo and Francesca Palumbo<\/p>\n

[C12] Adaptable AES Implementation with Power-Gating Support
\n<\/a>Authors:<\/strong>\u00a0 Subhadeep Banik, Andrey Bogdanov, Tiziana Fanni, Carlo Sau, Luigi Raffo, Francesca Palumbo and Francesco Regazzoni<\/p>\n

[J5] Power-Awarness in Coarse-Grained Reconfigurable Multi-Functional Architectures: a Dataflow Based Strategy
\n<\/a>Authors:<\/strong> Francesca Palumbo, Tiziana Fanni, Carlo Sau and\u00a0 Paolo Meloni<\/p>\n

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<\/a><\/p>\n

2015<\/strong><\/h3>\n

[C12] Power Modelling for Saving Strategies in Coarse Grained Reconfigurable Systems
\n<\/a>Authors:<\/strong>\u00a0 Tiziana Fanni, Carlo Sau, Paolo Meloni, Luigi Raffo and Francesca Palumbo<\/p>\n

[C11] Reconfigurable Coprocessors Synthesis in the MPEG-RVC Domain
\n<\/a>Authors:<\/strong> Carlo Sau, Luca Fanni, Paolo Meloni, Luigi Raffo and Francesca Palumbo<\/p>\n

[J4] Automated Design Flow for Multi-Functional Dataflow-Based Platforms<\/a><\/strong>
\nAuthors:<\/strong> Carlo Sau, Paolo Meloni, Luigi Raffo, Francesca Palumbo, Simone Casale-Brunet, Endri Bezati and Marco Mattavelli<\/p>\n

[J3] Early Stage Automatic Strategy for Power-Aware Signal Processing Systems<\/a>
\n<\/a>Authors:<\/strong> Carlo Sau, Nicola Carta, Francesca Palumbo and Luigi Raffo<\/p>\n

[C10] Automated Power Gating Methodology for Dataflow-Based Reconfigurable Systems
\n<\/a>Authors:<\/strong> Tiziana Fanni, Carlo Sau, Luigi Raffo and Francesca Palumbo<\/p>\n

[J2] Coarse-Grained Reconfiguration: Dataflow-Based Power Management<\/a><\/strong>
\nAuthors:<\/strong> Francesca Palumbo, Carlo Sau and Luigi Raffo<\/p>\n

\n

<\/a><\/p>\n

2014<\/strong><\/h3>\n

[C9] Power-Awarness in Coarse-Grained Reconfigurable Designs: a Dataflow Based Strategy<\/a><\/strong>
\nAuthors:<\/strong> Francesca Palumbo, Carlo Sau and Luigi Raffo<\/p>\n

[C8] Automatic Generation of Dataflow-Based Reconfigurable Co-processing Units<\/a><\/strong>
\nAuthors:<\/strong> Carlo Sau and Francesca Palumbo<\/p>\n

[C7] Automated Design Flow for Coarse-Grained Reconfigurable Platforms: an RVC-CAL Multi-Standard Decoder Use-Case<\/a><\/strong>
\nAuthors:<\/strong> Carlo Sau, Luigi Raffo, Francesca Palumbo, Endri Bezati, Simone Casale-Brunet and Marco Mattavelli<\/p>\n

[J1] The Multi-Dataflow Composer Tool: Generation of on-the-fly Reconfigurable Platforms<\/a><\/strong>
\nAuthors:<\/strong> Francesca Palumbo, Nicola Carta, Danilo Pani, Paolo Meloni and Luigi Raffo<\/p>\n

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<\/a><\/p>\n

2013<\/strong><\/h3>\n

[C6] A Coarse-Grained Reconfigurable Approach for Low-Power Spike Sorting Architectures<\/a><\/strong>
\nAuthors:<\/strong> Nicola Carta, Carlo Sau, Danilo Pani, Francesca Palumbo and Luigi Raffo<\/p>\n

[C5] A Coarse-Grained Reconfigurable Wavelet Denoiser Exploiting the Multi-Dataflow Composer Tool<\/a><\/strong>
\nAuthors:<\/strong> Nicola Carta, Carlo Sau, Francesca Palumbo, Danilo Pani and Luigi Raffo<\/p>\n

[C4] DSE and Profiling of Multi-Context Coarse-Grained Reconfigurable Systems<\/a><\/strong>
\nAuthors:<\/strong> Francesca Palumbo, Carlo Sau and Luigi Raffo<\/p>\n

\n

<\/a><\/p>\n

2012<\/strong><\/h3>\n

[C3] Multi-Purpose Systems: a Novel Dataflow-Based Generation and Mapping Strategy<\/a><\/strong>
\nAuthors:<\/strong> Jean-Francois Nezan, Nicolas Siret, Matthieu Wipliez, Francesca Palumbo and Luigi Raffo<\/p>\n

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<\/a><\/p>\n

2011<\/strong><\/h3>\n

[C2] The Multi-Dataflow Composer Tool: a Runtime Reconfigurable HDL Platform Composer<\/a><\/strong>
\nAuthors:<\/strong> Francesca Palumbo, Nicola Carta and Luigi Raffo<\/p>\n

\n

<\/a><\/p>\n

2010<\/strong><\/h3>\n

[C1] RVC: A Multi-Decoder CAL Composer Tool<\/a><\/strong>
\nAuthors:<\/strong> Francesca Palumbo, Danilo Pani, Emanuele Manca, Luigi Raffo, Marco Mattavelli and Ghislain Roquier<\/p>","protected":false},"excerpt":{"rendered":"

Year: 2010, 2011, 2012, 2013, 2014, 2015, 2016 2016 [C13] Power and Clock Gating Modelling in Coarse Grained Reconfigurable Systems Authors:\u00a0 Tiziana Fanni, Carlo Sau, Paolo Meloni, Luigi Raffo and Francesca Palumbo [C12] Adaptable AES Implementation with Power-Gating Support Authors:\u00a0 Subhadeep Banik, Andrey Bogdanov, Tiziana Fanni, Carlo Sau, Luigi Raffo, Francesca Palumbo and Francesco Regazzoni … Continua la lettura di Publications<\/span> →<\/span><\/a><\/p>\n","protected":false},"author":2529,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-1778","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/sites.unica.it\/rpct\/wp-json\/wp\/v2\/pages\/1778","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/sites.unica.it\/rpct\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/sites.unica.it\/rpct\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/sites.unica.it\/rpct\/wp-json\/wp\/v2\/users\/2529"}],"replies":[{"embeddable":true,"href":"https:\/\/sites.unica.it\/rpct\/wp-json\/wp\/v2\/comments?post=1778"}],"version-history":[{"count":48,"href":"https:\/\/sites.unica.it\/rpct\/wp-json\/wp\/v2\/pages\/1778\/revisions"}],"predecessor-version":[{"id":2494,"href":"https:\/\/sites.unica.it\/rpct\/wp-json\/wp\/v2\/pages\/1778\/revisions\/2494"}],"wp:attachment":[{"href":"https:\/\/sites.unica.it\/rpct\/wp-json\/wp\/v2\/media?parent=1778"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}